1. Field of the Invention
The present invention relates to a display device for displaying an image by inputting a digital video signal, and more particularly, such a display device having light emitting elements. Further, the present invention relates to electronic equipment that uses the display device.
2. Description of the Related Art
Hereinafter explained is a display device, which disposes a light emitting element at each pixel and displays an image by controlling the emission of them.
In the explanation throughout this specification, as light emitting elements used are elements (OLED elements) having a structure in which an organic compound layer, that emits light when an electric field is generated, is sandwiched between an anode and a cathode. However, the light emitting element of the present invention is not limited to this structure. Any element which emits light by impressing electric field between the anode and the cathode can freely be used.
A display device is constituted by a display and peripheral circuits for inputting signals to the display.
A structure of a display is shown in a block diagram of FIG. 17. In FIG. 17, a display 1700 is constituted by a source signal line driver circuit 1701, a gate signal line driver circuit 1702, and a pixel portion 1703. The pixel portion has pixels disposed in a matrix shape.
Thin film transistors (hereinafter referred to as TFTs) are arranged in each pixel of the pixel portion. Explanation is herein made on a method of placing two TFTs in each pixel and controlling light emitted from the light emitting element of each pixel.
FIG. 7 shows a structure of a pixel portion of a display. Source signal lines S1 to Sx, gate signal lines G1 to Gy, and power supply lines V1 to Vx are arranged in a pixel portion 700, and x columns and y rows (where x and y are natural numbers) of pixels are also placed in the pixel portion. Each pixel 800 has a switching TFT 801, a driver TFT 802, a storage capacitor 803, and a light emitting element 804.
A pixel of the pixel portion shown in FIG. 7 is shown magnified in FIG. 8. The pixel is constituted by one source signal line S of the source signal lines S1 to Sx, one gate signal line G of the gate signal lines G1 to Gy, one power supply line V of the power supply lines V1 to Vx, the switching TFT 801, the driver TFT 802, the storage capacitor 803, and the light emitting element 804.
A gate electrode of the switching TFT 801 is connected to the gate signal line G, and either a source region or a drain region of the switching TFT 801 is connected to the source signal line S, while the other is connected to a gate electrode of the driver TFT 802 and to one electrode of the storage capacitor 803. Either a source region or a drain region of the driver TFT 802 is connected to the power supply line V, while the other is connected to an anode or a cathode of the light emitting element 804. The power supply line V is connected to one of the two electrodes of the storage capacitor 803, namely the electrode on a side to which the driver TFT 802 and the switching TFT 801 are not connected.
The anode of the light emitting element 804 is referred to as a pixel electrode, and the cathode of the light emitting element 804 is referred to as an opposing electrode, within this specification for cases in which the source region or the drain region of the driver TFT 802 is connected to the anode of the light emitting element 804. On the other hand, if the source region or the drain region of the driver TFT 802 is connected to the cathode of the light emitting element 804, then the cathode of the light emitting element 804 is referred to as the pixel electrode, and the anode of the light emitting element 804 is referred to as the opposing electrode.
Further, a potential imparted to the power supply line V is referred to as a power source potential, and a potential imparted to the opposing electrode is referred to as an opposing potential.
The switching TFT 801 and the driver TFT 802 may be either p-channel TFTs or n-channel TFTs.
The storage capacitor 803 is not necessarily provided.
For instance, when an n-channel TFT used for the driver TFT 802 has an LDD region formed so as to overlap the gate electrode with a gate insulating film interposed, a parasitic capacitance called in general a gate capacitance is formed in this overlapping area. The parasitic capacitance may be used positively for a storage capacitor to store the voltage supplied to the gate electrode of the driver TFT 802.
Operations during display of an image with the aforementioned pixel structure are explained below.
A signal is inputted to the gate signal line G, and the potential of the gate electrode of the switching TFT 801 changes, then a gate voltage is changed. The signal is inputted to the gate electrode of the driver TFT 802 from the source signal line S, via source and drain of the switching TFT 801 which thus has been in a conductive state. Further, the signal is stored in the storage capacitor 803. The gate voltage of the driver TFT 802 changes in accordance with the signal inputted to the gate electrode of the driver TFT 802, then the source and drain are in a conductive state. The potential of the power supply line V is imparted to the pixel electrode of the light emitting element 804 through the driver TFT 802. The light emitting element 804 thus emits light.
A method of expressing gradations with pixels having such a structure is explained.
Gradation expression methods can be roughly divided into an analog method and a digital method. The digital method has advantages of being good at variation of TFTs and increasing gradations.
A time gradation method is known as an example of the digital gradation expression method. The time gradation driving method is a method of expressing gradations by controlling the period that each pixel of a display device emits light. (See a patent document 1)
If a period for displaying one image is taken as one frame period, then one frame period is divided into a plurality of subframe periods.
Turn on or turn off, namely whether the light emitting element of each pixel is made to emit light or not, is performed for each subframe period. Then, the period during which the light emitting element emits light in one frame period is controlled to express a gradation for each pixel.
The time gradation driving method is explained in detail using timing charts of FIG. 5. Note that an example of expressing gradation using a 4-bits digital image signal is shown in FIG. 5. Note also that FIG. 7 and FIG. 8 may be referred to regarding the structure of the pixels and the pixel portion. With an external power source (not shown in the figure), the opposing potential can be switched between a potential which is nearly the same as that of the power supply lines V1 to Vx (power source potential), and a potential which has a difference from the power supply lines V1 to Vx to an extent that the light emitting element 804 will emit light.
In FIG. 5A, one frame period F1 is divided into a plurality of subframe periods SF1 to SF4.
The gate signal line G1 is selected first in the first subframe period SF1, and a digital image signal is inputted from the source signal lines S1 to Sx to each of the pixels having the switching TFTs 801 with gate electrodes connected to the gate signal line G1. The driver TFT 802 of each pixel is placed in an ON state or an OFF state by the inputted digital image signal.
The term “ON state” for a TFT in this specification indicates that there is a conductive state between the source and the drain in accordance with the gate voltage. Further, the term “OFF state” for a TFT indicates that there is a non-conductive state between the source and the drain in accordance with the gate voltage.
The opposing potential of the light emitting elements 804 is herein set nearly equal to the potential of the power supply lines V1 to Vx (power source potential), and therefore the light emitting elements 804 do not emit light even in pixels having their driver TFT 802 in an ON state.
FIG. 5B is a timing chart which shows an operation for inputting digital image signals to the driver TFTs 802 of each pixel.
In FIG. 5B, S1 to Sx indicate the period in which a signal corresponding to each source signal line is sampled in a source signal line driver circuit (not shown in the figure). The signals sampled are simultaneously outputted to each source signal line during a fly-back period shown in the figure. The outputted signal is inputted to the gate electrode of the driver TFT 802 in a pixel selected by the gate signal line.
The aforementioned operations are repeated for all of the gate signal lines G1 to Gy, and a write-in period Ta1 is completed. Note that a period for write-in during the first subframe period SF1 is called Ta1. In general, a write-in period of the j-th subframe period (where j is a natural number) is called Taj.
The opposing potential changes when the write-in period Ta1 is completed, so as to have a potential difference from the power source potential to an extent that the light emitting element 804 will emit light. A display period Ts1 thus begins. Note that the display period of the first subframe period SF1 is called Ts1. In general, a display period of the j-th subframe period (where j is a natural number) is called Tsj. The light emitting element 804 of each pixel are placed in a light emitting state or a non-light emitting state, corresponding to the inputted signal, in the display period Ts1.
The above operations are repeated for all of the subframe periods SF1 to SF4, then, one frame period F1 is completed. The length of the display periods Ts1 to Ts4 of the subframe periods SF1 to SF4 can be set appropriately, and gradations are expressed by an accumulation of the display periods of the subframe period during which the light emitting elements 804 emit light. In other words, the total amount of the turn-on time within one frame period is used to express the gradations.
A method of generally expressing 2n gradations by inputting n-bit digital video signals, is explained. One frame period is divided into n subframe periods SF1 to SFn, for example, and the ratios of the lengths of the display periods Ts1 to Tsn of the subframe periods SF1 to SFn are set so as to be Ts1:Ts2: . . . :Tsn-1:Tsn=20:2−1: . . . : 2−n+2:2−n+1. Note that the lengths of the write-in periods Ta1 to Tan are all the same.
The gradation of the pixels in one frame period is determined by finding the total of the display period Ts during which a light emitting state is selected in the light emitting element 804. When n=8, for example, if the brightness for a case in which a pixel emits light during all of the display periods is taken to be 100%, a brightness of 1% can be expressed when the pixel emits light in the display periods Ts8 and Ts7. A brightness of 60% can be expressed when the pixel emits light in the display periods Ts6, Ts4, and Ts1.
Incidentally, a subframe period can be further divided into a plurality of subframe periods.
It is preferable that the display device has as little electric power consumption as possible here. Low electric power consumption is especially desirable if the display device is incorporated into a portable information device or the like to be utilized.
In this case, with respect to a display device, into which the 4 bit signal mentioned above is inputted to thereby display 24 gradations, a method of expressing gradations by using only the high 1-bit signal is used in order to reduce the electric power consumption of the display device. (See a patent document 2)
[Patent Document 1]
Japanese Patent Application Laid-open No. 2001-343933
[Patent Document 2]
Japanese Patent Application Laid-open No. Hei 11-133921
A timing chart showing a driving method of the display device in a first display mode of expressing 24 gradations is shown in FIG. 13A, and another timing chart showing a driving method of the display device in a second display mode of expressing gradations by using only the high 1-bit signal is shown in FIG. 13B.
One subframe period is sufficient for the driving method in the second display mode. Therefore, it is possible to make start pulses and clock pulses inputted to each driver circuit (source signal line driver circuit and gate signal line driver circuit) have a lower frequency, and to realize lower electric power consumption as compared with the driving method in the first display mode of expressing gradations of the high 1-bit.
When the accumulated length of write-in periods of the first display mode is longer than that of the second display mode, the proportion that an effective display period occupies per one frame period is increased by changing the voltage between a cathode and an anode of a light emitting element according to the display period.
However, the voltage inputted to each driver circuit is equal for both first and second display modes in such a display device, and it may not lead to lower electric power consumption.
An object of the present invention is to provide a display device in which electric power consumption is smaller, when performing drive in which the number of gradations expressed is reduced.